Semiconductor memory devices have been proposed that detect the transition of an external address supplied from outside a semiconductor memory device, refresh the memory cells indicated by a refresh address generated within the semiconductor memory device, and following completion of refreshing, perform a read/write operation in accordance with the external address. As can be seen in Japanese Unexamined Patent Application, First Publication No. Sho 61-5495 and Japanese Unexamined Patent Application, First Publication No. Hei 6-36557, a method was employed for the address access method in this type of semiconductor memory device that decodes the switched address after switching the external address and refresh address.
The following provides an explanation of the address access method employed in the background art with reference to FIGS. 15 and 16. FIG. 15 is a block diagram showing the structure of a semiconductor memory device according to the background art, while FIG. 16 is a timing chart showing the operation of each section.
In block BLn shown in FIG. 15, refresh address generation section 213 generates refresh address RXn for refreshing memory cells in word line units. In addition, address buffer 211 and refresh address buffer 214 buffer external address Xn, which is a partial bit of the row address of the external address used for selecting a word line, and the above refresh address RXn, and output internal address Xn′ and refresh address RXn′, respectively.
Multiplexer 218 selects either internal address Xn′ or refresh address RXn′ based on an external address transmission signal EXTR and refresh address transmission signal RFTR generated by refresh control circuit 217, and then outputs address XnM. Blocks BLn+1 and BLn+2 have the same compositions as block BLn, and output address Xn+1 M and Xn+2M, respectively. 1st address decoder 212 decodes these addresses and outputs decode signals X1Dm, X1Dm+1 and X1Dm+2. Block BLm is composed with the structural elements explained above, and is provided with block BLq and so forth that output decode signal X1D1q in the same manner.
Next, ATD (Address Transition Detector) 216 detects a change in the external address and outputs an address transition detection (hereinafter referred to as ATD) signal. Refresh control circuit 217 generates the above-mentioned external address transmission signal EXTR and refresh address transmission signal RFTR based on this address transition detection signal. Word driver 220 also serves as a decoder and performs decoding based on decode signals X1Dm and X1Dq to activate word line WLmq.
In this manner, in the semiconductor memory device of the background art, multiplexer 218, which performs switching of internal address Xn′ obtained from external address Xn and refresh address RXn′ obtained from refresh address RXn, is arranged between address buffer 211, refresh address buffer 214 and 1st address decoder 212.
The semiconductor memory device according to the above structure operates in the manner shown in FIG. 16. To begin with, a new access request is generated and external address changes from “A0” to “A1” at time t201. Whereupon, ATD216 detects this change and generates an ATD signal, and refresh control circuit 217 changes external address transmission signal EXTR and refresh address transmission signal RFTR for refreshing the memory cells corresponding to memory address “R0” to the low level (abbreviated as “L”) and high level (abbreviated as “H”), respectively.
As a result, multiplexer 218 selects refresh address RXn′, refresh address RXn′ is output as address XnM at time t202 after a multiplexer delay due to the selection operation, and addresses Xn+1M and Xn+2M are output in the same manner. 1st address decoder 212 then decodes these addresses, outputs decode signals X1Dm, X1Dm+1 and X1Dm+2 at time t203 after a delay due to the decoding operation, and decode signal X1Dq is output from block BLq in the same manner. Subsequently, the word line corresponding to the external address is deactivated at time t204, and pre-charging of the bit line is performed until time t205. The above decode signals are decoded by word driver 220, and the refresh operation then begins with the activation of the word line corresponding to refresh address RXn′ at time t205 after a delay for that operation.
Later at time t206, refresh control circuit 217 changes external address transmission signal EXTR and refresh address transmission signal RFTR for a read/write operation with respect to external address Xn to “H” and “L”, respectively. As a result, multiplexer 218 selects internal address Xn on the external address side, and the address selected at time t207 after a delay for the operation of multiplexer 218 is output as address XnM. 1st address decoder 212 then performs decoding in the same manner as above, and a decode signal is output at time t208 after a delay for the decoding operation. Subsequently, at time t209, the word line corresponding to refresh address RXn′ is deactivated, and pre-charging of the bit line is performed until time t210. Word driver 220 then decodes the decode signals output from blocks B1m and B1q, activates the word line corresponding to external address Xn at time t210 after delay for this operation, and then starts the read/write operation. The operation starting at time t211 then repeats the same operation as described above.
In this manner, in the address access method employed by the semiconductor memory device according to the background art, as shown in FIG. 16, the delay time from the time the internal operation of the semiconductor memory devices switches from refresh to the read/write operation (time t206) to the time the word line for the read/write operation is selected (time t210) is the sum of the respective delay times of {circle around (1)} the multiplexer delay required for the switching operation of multiplexer 218, {circle around (2)} the delay of the 1st address decoder, and {circle around (3)} the delay of the word driver. Consequently, address access with respect to an external address (namely, until data DQ (A1) of the memory cells is obtained for the IO (input-output) output at time t212 from the time of switching from the refresh address to the external address at time t206) has the problem of being slow.
This applies similarly to when internal operation of the semiconductor memory device switches from read/write to refresh, and due to the delay in the timing by which the refresh operation is started, there is the problem of the completion of the refresh operation and the subsequent read/write operation being prolonged. In addition, although the above explanation provided a description of the case in which a read/write operation is performed after a refresh operation in which a change in the external address is used as a trigger, the same problems are encountered in the case in which a refresh operation is performed after a read/write operation using a change in the external address as a trigger.
Although this can also present a problem in the case of general-purpose DRAM as well, this is particularly a problem in terms of realizing a semiconductor memory device having general-purpose SRAM specifications that uses DRAM cells. Despite this, in general-purpose DRAM and so forth, since the refresh operation is not accompanied by a read/write operation and the read/write operation is not accompanied by a refresh operation, the above delay in address access does not present that much of a problem.
On the other hand, since the latter semiconductor memory device has general-purpose SRAM specifications, although the refresh operation cannot be recognized from outside the semiconductor memory device, it is necessary to perform the refresh operation regularly inside the semiconductor memory device. As one example for realizing this, the refresh operation using a change in the external address as a trigger and its following read/write operation may be performed according to time-sharing within a single memory cycle. In this structure, two operations in the form of a refresh operation and read/write operation are performed within a single memory cycle, and accompanying this, a decode operation and refresh address/external address selection operation are each performed twice.
In other words, in the case of comparing with general-purpose DRAM, in terms of simple calculations, twice the internal operations are performed in the latter semiconductor memory device, and this device is subject to even stricter conditions in terms of timing. In order to shorten the memory cycle and achieve faster operation in the semiconductor memory device, it is necessary to not only accelerate the refresh operation and read/write operation, but also reduce the time required for each operation other than these operations (e.g., decode operation).
In addition, the above problem may also arise for semiconductor memory devices equipped with spare memory cells. In recent years, measures for remedying failures have come to be commonly deployed in DRAM and other semiconductor memory devices for the purpose of remedying manufacturing defects present in memory cell arrays and improving yield. Namely, in this type of semiconductor memory devices, the memory cell array employs a redundant structure in which a spare memory cell array (to be referred to as a “spare cell array”) for remedying failures by replacing a failed region in the inherently provided memory cell array (to be referred to as the “normal cell array”) for reading or writing data is provided in addition to the normal cell array.
Although defects in the normal cell array may occur in individual memory cell units, there are many cases in which they occur linearly in “line” units such as word lines or bit line pairs. Consequently, in the remedying of failures of the normal cell array, the defective line or memory cell in the normal cell array is replaced with a line or memory cell of a spare cell array. This being the case, in the case there is an access request for a failed line or memory cell in the normal cell array, access is performed after switching to the line or memory cell in the spare cell array.
FIG. 17 is a block diagram showing the essential portion of the structure of a semiconductor memory device according to the background art. In this drawing, the structure of a semiconductor memory device represented by the DRAM and so forth described in Japanese Unexamined Patent Application, First Publication No. 2000-11681 is depicted in simplified form to facilitate understanding. In the drawing, memory cell array 250 is composed of a plurality of memory cells that require periodical refreshing in order to retain data. In addition, memory cell array 250 is composed of normal cell array 251 that is normally used for access, and spare cell array 252 for remedying failures.
Next, refresh counter 253 successively generates a refresh address REF_ADD for refreshing memory cell array 250. Multiplexer 254 selects either external address EXT_ADD or refresh address REF_ADD in accordance with a switching signal not shown, and outputs address MUX_ADD. Furthermore, as was previously described, external address EXT_ADD is an access address given from outside a semiconductor memory device accompanying a read or write request.
Next, program circuit 255 stores replacement information that indicates which line in spare cell array 252 replaces a failed line in normal cell array 251. In the case address MUX_ADD is given, program circuit 255 respectively generates a killer signal KL for suppressing selection of a line in normal cell array 251, and a redundancy selection signal RDN_ADD for selecting a line in spare cell array 252 that is used in the case of performing replacement.
Here, killer signal KL and redundancy selection signal RDN_ADD are both validated in the case a line in normal cell array 251 is replaced with a line in spare cell array 252. Consequently, decoder 256 does not generate a decode signal for selecting a line in normal cell array 251, and a normal side word driver not shown does not activate any line in normal cell array 251. Instead, a spare side word driver not shown activates a corresponding line in spare cell array 252 in accordance with redundancy selection signal RDN_ADD.
On the other hand, in the case a line in normal cell array 251 is not replaced with a line in spare cell array 252, both killer signal KL and redundancy selection signal RDN_ADD are invalidated. Consequently, decoder 256 generates a decode signal by decoding address MUX_ADD, and the normal side word driver activates a corresponding line in normal cell array 251 in accordance with this decode signal. At this time, the spare side word driver does not activate any line in spare cell array 252 since redundancy selection signal RDN_ADD has been invalidated.
As described above, in the semiconductor memory device according to the background art equipped with a spare memory cell, similar to that shown in FIG. 15, a decoder 256 is arranged at the latter stage of the multiplexer 254. The reason for the semiconductor memory device according to the background art employing this structure is to be able to share program circuit 255 and decoder 256 between the case in which memory cell array 250 is accessed with external address EXT_ADD and the case in which memory cell array 250 is refreshed with refresh address REF_ADD.
However, when such a structure is employed, in the case of accessing memory cell array 250 using, for example, external address EXT_ADD, the problem occurs in which access becomes slow and cycle time becomes longer for the same reasons as previously mentioned. Namely, in the structure of FIG. 17, after the value of external address EXT_ADD and its accompanying address MUX_ADD are defined, decoder 256 decodes address MUX_ADD and the normal side word driver activates memory cell array 250. In other words, the series of operations consisting of address definition, selection of external address or refresh address, decoding of the selected address and activation of the word line can all only be carried out in succession.